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HIGH-VOLTAGE MIXED-SIGNAL IC
65COM x 132SEG Matrix LCD Controller-Driver
Product Specifications Version 1.32
September 24, 2003
ULTRACHIP
The Coolest LCD Driver. Ever!!
UC1606
65x132 Matrix LCD Controller-Drivers
TABLE OF CONTENT
Introduction .........................................................................................................1 Ordering Information ..........................................................................................2 Block Diagram.....................................................................................................3 Pin Description....................................................................................................4 Control Registers................................................................................................7 Command Table ..................................................................................................9 Command description ......................................................................................10 LCD Voltage Settings .......................................................................................15 LCD Display Controls .......................................................................................18 Host Interface ....................................................................................................20 Display Data RAM .............................................................................................24 Reset & Power Management ............................................................................27 Absolute Maximum Ratings .............................................................................31 Specifications....................................................................................................32 AC Characteristics............................................................................................33 Physical Dimensions ........................................................................................37 Alignment Mark Information ............................................................................38 Pad Coordinates ...............................................................................................39 Tray Information................................................................................................42 Revision History................................................................................................43
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UC1606
65x132 Matrix LCD Controller-Drivers
UC1606
Single-Chip, Ultra-Low Power Passive Matrix LCD Controller-Driver
* Support industry standard 8-bit parallel interface (8080 or 6800), 4-wire SPI (S8), and 3-wire SPI (S9) serial interface. Support four multiplexing rates (25, 33, 49, 65). Self-configuring 6x charge pump with onchip pumping capacitor requires only 3 external capacitors to operate. Flexible data addressing/mapping schemes to support wide ranges of software models and LCD layout placements. Software programmable 4 temperature compensation coefficients. On-chip bypass capacitor for VLCD makes VLCD bypass capacitor optional for small LCD panels. On-chip Power-ON Reset and Software RESET commands, make RST pin optional. VDD (digital) range: 2.4V ~ 5V VDD (analog) range: 2.4V ~ 5V 6.5V ~ 12.5V LCD VOP range: Available in gold bump dies Bump pitch: 70uM min. Bump gap: 24uM min.
INTRODUCTION
UC1606 is an advanced high-voltage mixedsignal CMOS IC, especially designed for the display needs of ultra-low power hand-held devices. This chip employs UltraChip's unique DCC (Direct Capacitor Coupling) driver architecture to achieve near crosstalk free images. In addition to low power COM and SEG drivers, UC1606 contain all necessary circuits for high-V LCD power supply, bias voltage generation, timing generation and graphics data memory. Advanced circuit design techniques are employed to minimize external component counts and reduce connector size while achieving extremely low power consumption. MAIN APPLICATIONS * Cellular Phones, Smart Phones, and other battery operated devices and/or portable Instruments * * *
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FEATURE HIGHLIGHTS * Single chip controller-driver supports 65 COM x 132 SEG LCD.
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Version 1.32
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003
ORDERING INFORMATION
Product ID UC1606XGAF Description 65 COM x 132 SEG LCD driver
General Notes
APPLICATION INFORMATION For improved readability, the specification contains many application data points. When application information is given, it is advisory and does not form part of the specification for the device. BARE DIE DISCLAIMER All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of UltraChip's delivery. There is no post waffle saw/pack testing performed on individual die. Although the latest modern processes are utilized for wafer sawing and die pick-&-place into waffle pack carriers, UltraChip has no control of third party procedures in the handling, packing or assembly of the die. Accordingly, it is the responsibility of the customer to test and quality their application in which the die is to be used. UltraChip assumes no liability for device functionality or performance of the die or systems after handling, packing or assembly of the die. LIFE SUPPORT APPLICATIONS These devices are not designed for use in life support appliances, or systems where malfunction of these products can reasonably be expected to result in personal injuries. Customer using or selling these products for use in such applications do so at their own risk.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
BLOCK DIAGRAM
COLUMN ADDRESS GENERATOR PAGE ADDRESS GENERATOR ROW ADDRESS GENERATOR
DATA RAM I/O BUFFER
POWER-ON & RESET CONTROL
LEVEL SHIFTER
CLOCK & TIMING GEN.
DISPLAY DATA RAM
CONTROL & STATUS REGISTER
DISPLAY DATA LATCHES COMMAND HOST INTERFACE LEVEL SHIFTERS SEG DRIVERS VLCD & BIAS GENERATOR CL
CB0
CB1
COM DRIVERS
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High-Voltage Mixed-Signal IC
(c)1999-2003
PIN DESCRIPTION
Name Type Pins MAIN POWER SUPPLY VDD VDD2 VDD3 VSS VSS2 VDD2/VDD3 is the analog power supply and it should be connected to the same power source. VDD is the digital power supply and it should be connected to a voltage source that is no higher than VDD2/VDD3. Minimize the trace resistance for VDD and VDD2/VDD3. GND Ground. Connect VSS and VSS2 to the shared GND pin. Minimize the trace resistance for VSS and VSS2. LCD POWER SUPPLY LCD Bias Voltages. These are the voltage sources to provide SEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VBX+ and VBX-. The resistance of these four traces directly affects the SEG driving strength of the resulting LCD module. Minimize the trace resistance is critical in achieving high quality image. Main LCD Power Supply. Connect these pins together. PWR A by-pass capacitor CL is optional. When CL is used, connect CL between VLCD and VSS, and keep the trace resistance under 300 Ohm. Description
PWR
VB1+ VB1- VB0+ VB0-
PWR
VLCD-IN VLCD-OUT
NOTE * In COG applications, use one maximum width trace to connect VDD/VDD2/VDD3 to the LCM pad to minimize trace resistance. However, to avoid noise cross-coupling, insert a slit, 0.2~0.3mm long, between VDD/VDD2/VDD3. Same treatment for VSS/VSS2. Recommended capacitor values: CB: 150 ~ 250x LCD load capacitance or 1.0uF (2V), whichever is higher. CL: 5nF ~ 20nF (16V) is appropriate for most applications.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
Name
Type
Pins CONFIGURATION PIN Multiplex Rate selection "LL": 25 "HL": 49
Description
MR[1:0] BR[1:0] TC[1:0]
I I I
"LH": 33 "HH": 65
LCD Bias Ratio. Four bias ratios are supported for each MR setting. Temperature Compensation selection "LL": -0.0% "HL": -0.1% Parallel/Serial. Serial modes: Parallel modes: "LH": -0.05% "HH": -0.2% HOST INTERFACE
PS[1:0] CS0 CS1 RST CD
I
"LL": serial (S8) "HL": 8080
"LH": serial (S9) "HH": 6800
I I I
Chip Select. In parallel mode and S8 mode, chip is selected when CS0="L" and CS1="H". When the chip is not selected, D[7:0] may be high impedance. *1 When RST="L", all control registers are re-initialized by their default states. When RST is not used, connect the pin to VDD. Select Command or Display Data for read/write operation. CD pin is not used in S9 modes, connect it to VDD or VSS. "L": Command "H": Display data WR[1:0] controls the read/write operation of the host interface. In parallel mode, WR[1:0] meaning depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used. Connect to VSS. Bi-directional bus for both serial and parallel host interfaces. In S8 and S9 mode, leave unused pins open-circuit.
WR0 WR1
I
D0~D7
I/O
D0 D1 D2 D3 D4 D5 D6 D7
PS=1x D0 D1 D2 D3 D4 D5 D6 D7
PS=0x SCK SDA
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High-Voltage Mixed-Signal IC
(c)1999-2003 Description LCD DRIVER OUTPUT SEG (column) driver outputs. Support up to 132 columns. Leave unused drivers open-circuit. Icon driver output. COM (row) driver outputs. Support up to 64 rows. When Mux Rate is not 65, please use only COM1~COM(x-1), x=65, 49, 33, or 25, and leave COM (x) ~ COM64 open-circuit. MISC. PINS Auxiliary VDD. These pins are connected to the main VDD bus on chip, and they are provided to facilitate chip configurations in COG and COF applications. There is no need to connect VDDX to VDD externally. These pins should not be used to provide VDD power to the chip. Reserved. Leave this pin open circuit. Test control. Connect to VSS. Test I/O pins. Leave these pins open circuit during normal use. Test control. Leave these pins open circuit during normal use.
Name SEG1 ~ SEG132 CIC COM1 ~ COM64
Type
Pins
HV HV HV
VDDX EO TST4 TST[3:1] TP[3:1]
O
O I I/O I
*1 When read data is needed under joint bus (using more than one UC1606), following application circuits are recommended. Each R/W (RD) pin should be separated from others.
(UC1606)U1
CS0 CS1 R/W E
(UC1606)U1
CS0 CS1 R/W E
(UC1606)U1
CS0 CS1 RD WR
(UC1606)U1
CS0 CS1 RD WR
VDD CS (R/W)1 E (R/W)2 CS
VDD RD1 WR RD2
For 6800 Mode
For 8080 Mode
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
CONTROL REGISTERS
UC1606 contains registers which control the chip operation. These registers can be modified by commands. The following table is a summary of the control registers, their meaning and their default value. The commands supported by UC1606 are described in the next two sections, first a summary table, followed by a detailed description. Name: Default: Name SL CR CA PA BR The Symbolic reference of the register byte. Note that, some symbol names refer to collection of bits (flags) within one register byte. Numbers shown in Bold fonts are values after Power-Up-Reset and System-Reset. Bits 6 8 8 4 2 Default 0H 0H 0H 0H PIN Description Start Line. Mapping from COM1 to Display Data RAM. Return Column Address. Useful for cursor implementation. Display Data RAM Column Address (Used in Host to Display Data RAM access) Display Data RAM Page Address (Used in Host to Display Data RAM access) Bias Ratio. The ratio between VLCD and VBIAS. Mux Rate 65 49 33/25 Bias Ratio (BR[1:0]) 00 01 10 11 7.33 8.0 8.66 9.33 6.0 6.67 7.33 8.0 4.67 5.33 6.0 6.66
Default value depends on BR[1:0] pin configuration, and can be re-defined by Set LCD Bias Ratio command. TC 2 PIN Temperature Compensation (per C). 00b: 0.0% 01b: -0.05% 10b: -0.1% 11b: -0.2% Default value depends on TC[1:0] pin configuration. Gain, coarse setting of VBIAS and VLCD GN[2:0] 000 001 010 011 100 101 110 111 Gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72 PM MR 6 2 10H PIN Electronic Potentiometer to fine tune VBIAS and VLCD Multiplexing Rate: Number of pixel rows: 00b: 25 01b: 33 10b: 49 11b: 65 Default value depends on MR[1:0] pin configuration.
o
GN
3
3H
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High-Voltage Mixed-Signal IC
(c)1999-2003 Description Operating Modes (Read Only) 10b: Sleep 11b: Normal 01b: (Not used) 00b: Reset Busy with internal processes (reset, changing mode, etc.) OK for Display RAM read/write access. Reset in progress, Host Interface not ready Vlcd pump control. PC[0]: PC[2:1]: 0b:Low LCD loading 00b: External Vlcd 10b: 5x 1b: Regular LCD loading 01b: 4x 11b: 6x
Name OM
Bits 2
Default -
BZ RS PC
1 1 3
-
7H
APC0 DC
8 3
6CH 0H
Advanced Product Configuration. For UltraChip only. Please do not use. Display Control: DC[0]: PXV: Pixels Inverse (Default: OFF) DC[1]: APO: All Pixels ON (Default:: OFF) DC[2]: Display ON/OFF (Default:: OFF).
AC
4
0H
Address Control: AC[0]: WA: Automatic column/page Wrap Around (Default 0:OFF) AC[1]: Reserved (always set to 0) AC[2]: PID: PA (page address) auto increment direction (0: +1 1: -1) AC[3]: CUM: Cursor update mode, (Default 0:OFF) when CUM=1, CA increment on write only, wrap around suspended
LC
4
0H
LCD Mapping Control: LC[0]: MSF: MSB First mapping Option LC[1]: Reserved (always set to 0) LC[2]: MX, Mirror X (Column sequence inversion) LC[3]: MY, Mirror Y (Row sequence inversion)
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
COMMAND TABLE
The following is a list of host commands supported by UC1606 C/D: W/R: 0: Control, 0: Write Cycle, 1: Data 1: Read Cycle
# Useful Data bits - Don't Care
Command 1 2 3 4 5 6 7 8 9 Write Data Byte Read Data Byte Get Status Set Column Address LSB Set Column Address MSB Set Gain Set Pump Control Set Adv. Product Config. (double byte command) C/D W/R D7 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 # # BZ 0 0 0 0 0 # 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # D6 # # MX 0 0 0 0 0 # 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 # D5 # # DE 0 0 1 1 1 # # 1 0 # 0 1 1 1 1 0 1 1 1 1 1 1 # D4 # # RS 0 1 0 0 1 # # 1 0 # 0 0 0 0 0 0 0 0 0 0 0 0 # D3 # # 0 # # 0 1 0 # # # 0 # 1 0 0 0 1 # 0 0 1 1 1 0 # D2 # #
0
D1 # #
0
D0 # # 0 # # # # R # # # 1 # # # # # # # 0 1 # 0 1 TT #
Action Write 1 byte Read 1 byte Get Status Set CA[3:0] Set CA[7:4] Set GN[2:0] Set PC[2:0] For UltraChip only. Do not use. Set SL[5:0] Set PA[3:0] Set PM[5:0] Set AC[2:0] Set LC[3] Set DC[1] Set DC[0] Set DC[2] Set LC[3:0] System Reset No operation Set BR[1:0] AC[3]=0, CA=CR AC[3]=1, CR=CA For UltraChip only. Do not use.
Default value N/A N/A N/A 0 0 011b 111b N/A 0 0 PM=16 000b 0 0=disable 0=disable 0=disable 0 N/A N/A PIN N/A N/A N/A
# # # # 0 # # # 0 # # 0 1 1 1 # 0 0 0 1 1 1 #
# # # # 0 # # # 0 # 0 0 0 1 1 0 1 1 # 1 1 #
Set Start Line Set Page Address Set Potentiometer 10 (double-byte command) 11 Set RAM Address Control 12 Set Column Mirroring 13 14 15 16 17 18 Set All-Pixel-ON Set Inverse Display Set Display Enable Set LCD Mapping Control System Reset NOP
19 Set LCD Bias Ratio 20 Reset Cursor Mode 21 Set Cursor Mode 22 Set Test Control (double byte command)
* Other than commands listed above, all other bit patterns may result in undefined behavior.
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003
COMMAND DESCRIPTION
(1) Write data to display memory Action Write data (2) Read data to display memory Action Read data C/D W/R D7 1 1 D6 D5 D4 D3 D2 D1 D0 8bits data from SRAM C/D W/R D7 1 0 D6 D5 D4 D3 D2 D1 D0 8bits data write to SRAM
Write/Read Data Byte (command 1,2 ) operation accesses display buffer RAM based on Page Address (PA) register and Column Address (CA) register. To minimize bus interface cycles, PA and CA will be increased or decreased automatically depending on the setting of Access Control (AC) registers. PA and CA can also be programmed directly by issuing Set Page Address and Set Column Address commands. If Wrap-Around (WA) is OFF (AC[0] = 0), CA will stop increasing after reaching the end of page (MC), and system programmers need to set the values of PA and CA explicitly. If WA is ON (AC[0]=1), when CA reaches end of page, CA will be reset to 0 and PA will be increased or decreased by 1, depending on the setting of Page Increment Direction (PID, AC[2]). When PA reaches the boundary of RAM (i.e. PA = 0 or 31), PA will be wrapped around to the other end of RAM and continue. (3) Get Status Action Get Status Status flag definitions: BZ: Busy with internal process. When BZ=1 host interface can access if RS=0. MX: Status of register LC[2], mirror X. DE: Display enable flag. DE=1 when display enabled RS: Reset in progress. If RS=1, host interface will be inaccessible. (4) Set Column Address Action Set Column Address LSB CA[3:0] C/D W/R D7 0 0 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CA3 CA2 CA1 CA0 C/D W/R D7 0 1 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 BZ MX DE RS
0 0 0 1 CA7 CA6 CA5 CA4 Set Column Address MSB CA[7:4] 0 0 Set the SRAM column address before Write/Read memory from host interface. CA possible value=0-131 (5) Set Gain Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 Set Gain GN[2:0] 0 0 Program Gain (GN[2:0]) . See section LCD VOLTAGE SETTING for more detail. GN2 GN1 GN0
GN[2:0] 000 001 010 011 100 101 110 111 Gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
(6) Set Pump Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 PC2 PC1 PC0 Set Pump Control PC[2:0] 0 0 Set PC[2:0] to program to use internal charge pump of external VLCD source: PC[0]: PC[2:1]: 0b: Low LCD loading 00b: External VLCD 10b: 5x 1b: Regular LCD loading 01b: 4x 11b: 6x
(7) Set Advance Product Configuration Action Set APC[0] (Double byte command) For UltraChip only. Please do NOT use. C/D W/R D7 0 0 0 0 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 R
APC register parameter
(8)
Set Start Line Action C/D W/R D7 0 0 0 D6 1 D5 D4 D3 D2 D1 D0 SL5 SL4 SL3 SL2 SL1 SL0
Set Start Line SL[5:0] Set the start line number
Start line setting will scroll the displayed image up by SL rows. The valid value is between 0 (no scrolling) and 63. One example of the visual effect on LCD is illustrated in the figure below.
Image row 0 .......... Image row N .......... Image row 63
0
0
N
Image row N ..........
N
Image row 0 ......... image row N-1
Image row 63
SL=0 COM Icon (CIC) is not affected by this command. (9) Set Page Address Action Set Page Address LSB PA [3:0] Effective range of value = 0 ~ 8 C/D W/R D7 0 0 1 D6 0 D5 1
SL=N
D4 1
D3
D2
D1
D0
PA3 PA2 PA1 PA0
Set the SRAM page address before write/read memory from host interface.
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High-Voltage Mixed-Signal IC
(c)1999-2003
(10) Set Potentiometer Action Set Potentiometer PM [5:0] (Double byte command) C/D W/R D7 0 0 0 0 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
PM5 PM4 PM3 PM2 PM1 PM0
Program Potentiometer (PM[5:0]). See section LCD VOLTAGE SETTING for more detail. Effective range of PM value = 0 ~ 63 (11) Set RAM Address Control Action Set AC [2:0] C/D W/R D7 0 0 1 D6 0 D5 0 D4 0 D3 1 D2 D1 D0 AC2 AC1 AC0
Program registers AC[2:0] for RAM address control. AC[0] -- Automatic column/page wrap around (WA). AC[1] - Reserved. (Always set to 0). AC[2] - PID, page address (PA) auto increment direction ( 0/1 = +/- 1 ) The column address will be reset to 0 and page address will increase/decrease (+/- 1 depend on PID = 0/1 ) after column address equal to maximum column value. (12) Set Column Mirroring Action Set Column Mirroring LC [3] Set LC[2] for COM (row) mirror (MY). C/D W/R D7 0 0 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 MY
MY is implemented by reversing the mapping order between RAM and COM (row) electrodes. The data stored in RAM is not affected by MY command. MY will have immediate effect on the display image. (13) Set All Pixel ON Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 0 DC1 Set All Pixel ON DC [1] 0 0 Set DC[1] to force all SEG drivers to output ON signals. This function has no effect on the existing data stored in display RAM. (14) Set Inverse Display(PXV) Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 0 1 1 DC0 Set Inverse Display DC [0] 0 0 Set DC[0] to force all SEG drivers to output the inverse of the data which stored in display memory. This function has no effect on the existing data stored in display RAM. (15) Set Display Enable Action C/D W/R D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 DC2 Set Display Enable DC[2] 0 0 This command is for programming registers DC[2].
When DC[2] is set to 1, UC1606 will turn on COM drivers and SEG drivers.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
(16) Set LCD Mapping Control Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 MY MX LC1 MSF Set LCD Mapping Control LC[3:0] 0 0 Set LC[3:0] for COM (row) mirror (MY), SEG (column) mirror (MX) and MSB first or LSB first options (MSF). MY is implemented by reversing the mapping order between RAM and COM (row) electrodes. The data stored in RAM is not affected by MY command. MY will have immediate effect on the display image. MX is implemented by selecting the CA or 131-CA as write/read(from host interface) display RAM column address so this function will only take effect after rewriting the RAM data LC1 - Reserved. (Always set to 0). MSF is implemented by MSB-LSB swapping. When MSB first (LC[0] ) bit is set, data D[7:0] will be realigned then stored to RAM. (17) System Reset Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 0 0 1 System Reset 0 0 This command will activate the system reset. The system will take about 5ms to reset (18) NOP Action C/D W/R D7 0 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 No operation 0 This command is used for "no operation". (19) Set LCD Bias Ratio Action Set Bias Ratio BR [1:0] Bias ratio definition: C/D W/R D7 0 0 1 D6 1 D5 1 D4 0 D3 1 D2 0 D1 D0 BR1 BR0
Mux Rate 65 49 33/25
Bias Ratio (BR[1:0]) 00 01 10 11 7.33 8.0 8.66 9.33 6.0 6.67 7.33 8.0 4.67 5.33 6.0 6.66
(20) Reset Cursor Mode Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 1 0 1 1 1 Return to cursor. AC[3]=0, CA=CR 0 0 This command is used to reset cursor update mode function. See description below.
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High-Voltage Mixed-Signal IC
(c)1999-2003
(21) Set Cursor Mode Action C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 1 1 1 1 Set AC[3]=1 CR=CA 0 0 Set Cursor Mode command is used to turn on cursor update mode function. AC[3] will be set to 1, register CR will be set to the value of register CA When AC[3]=1, column address (CA) will only increment with write RAM operation but not on read RAM operation. The address CA wraps around will also be suspended no matter what WA setting is. The purpose of this combination of features is to support "Read-Modify-Write" for cursor implementation. Reset Cursor Mode command will clear cursor update mode flag (AC[3]=0), CA will be restored to previous CA value which is stored in CR, and CA, PA increment will return to its normal condition.
(22) Set Test Control Action Set TT (Double byte command) C/D W/R D7 0 0 1 D6 1 D5 1 D4 0 D3 0 D2 1 D1 D0 TT
0 0 Testing parameter This command is used for UltraChip production testing. For UltraChip Only. Please do not use.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
LCD VOLTAGE SETTINGS
MULTIPLEX RATES Four multiplex rates are supported in UC1606 (65, 49, 33, 25). MR is not software programmable. It is determined by pin programming. BIAS SELECTION Bias Ratio (BR) is defined as the ratio between VLCD and VB, i.e. BR = VLCD/VB, where VB = VB1+ - VB1- = VB0+ - VB0-. The reference Bias Ratio can be estimated by: VREF Temperature Compensation VREF is a temperature compensated reference voltage. VREF increases automatically as ambient temperature cools down. Four (4) different temperatures compensated VREF can be selected via pin wiring. The compensation coefficient is given by the following table: TC[1:0] % per C
o
00 0.0
01 -0.05
10 -0.10
11 -0.20
Mux + 1
UC1606 supports four bias ratios for each MR (Mux Rate) setting as illustrated below. Bias Ratio (BR[1:0]) Mux Rate 65 49 33/25 00 7.33 6.0 4.67 01 8.0 6.67 5.33 10 8.66 7.33 6.0 11 9.33 8.0 6.66
Table 3: Temperature Compensation For all TC values, VREF are normalized to 1.25V at 25 oC. When selecting TC, make sure VB+ and VLCD stays within specified UC1606 ratings across entire operating temperature range. VLCD SELECTION VLCD may be supplied either by internal charge pump or by external power supply. The source of VLCD is controlled by PC[2:1]. When VLCD is generated internally its value has the following relationship with VB:
Table 1: BR vs. Mux Rates BR can be selected either by software program or by hardware pin wiring. VB GENERATION VB is generated internally by UC1606. The value of VB is determined by three control registers: GN (Gain), PM (Potential Meter), TC (Temperature Compensation) with the following relationship:
V LCD = BiasRatio x V B
Given VREF = 1.25V at 25 C, VLCD becomes:
o
V LCD BiasRatio x Gain x
600 + PM x 1.25 (1) 1200
When PM=0, then equation (1) becomes:
V B = Gain x V PM
where VPM is the output of an internal Electronic Potential Meter. The value of VPM is given by:
V LCD BiasRatio x Gain
LOAD DRIVING STRENGTH
1 .6
(1b)
VPM =
600 + PM x V REF 1200
UC1606's drivers and power supply circuits are designed to handle capacitance load of >2.5pF per pixel at VLCD=10.5V when VDD2 > 2.4V. UC1606 load driving strength is sensitive to ITO impedance of power supply circuits (VDD, VSS, VB0/B1, VLCD.) Be sure to minimize these ITO trace resistance for COG applications. POWER SUPPLY CONFIGURATION UC1606 has built-in charge pump with on-chip pumping capacitors. The number of pump stages can be programmed by setting PC[2:1] register. Make sure the chip is in Reset mode before changing the value of PC[2:0]. Given the same display quality, the lower PC[2:1] setting the more efficient is UC1606, but the weaker is the driving strength. In application,
The value of Gain is controlled by GN[2:0]. Their relationship is shown below: GN[2:0] 000 001 010 011 100 101 110 111 Gain 1.43 1.58 1.72 1.89 2.08 2.28 2.49 2.72 Table 2: Gain vs. GN value
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High-Voltage Mixed-Signal IC
(c)1999-2003 controllers when using internal VLCD generator. On the other hand, caution must be exercised when external VLCD source is used. The general rule of thumb is to make sure Display Enable is OFF before connecting or disconnecting external VLCD sources.
designers are recommended to verify the design with the highest setting first before trying lower settings to achieve better efficiency. Due to the use of fully embedded power supply, built-in power ready detector, and drain circuit, there is no rigid power up or power down sequences for UC1606
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
HI-V GENERATOR AND BIAS REFERENCE CIRCUIT
VDD
VDD VDD2 VDD3
VB0+ CB0 VB0VB1+ CB1
UC1606
VB1-
VLCDOUT VSS VSS2 VLCDIN CL RL (OPTIONAL)
FIGURE 1: Reference circuit using internal Hi-V generator circuit
VDD
VDD VDD2 VDD3
VB0+ CB0 VB0VB1+ CB1
UC1606
VB1-
VLCDOUT VSS VSS2 VLCDIN CL EXTERNAL VLCD SOURCE RL (OPTIONAL)
FIGURE 2: Reference circuit using external Hi-V source Note Recommended component values: * CB: ~100x LCD load capacitance or 1.0uF (2V), whichever is higher. CL: 5nF ~ 20nF (16V) is appropriate for most applications. RL: 10M. Acts as a draining circuit when the power is abnormally shut down. * The illustrated resistor values are for reference only. Please optimize for specific requirements of each application.
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High-Voltage Mixed-Signal IC
(c)1999-2003
LCD DISPLAY CONTROLS
CLOCK & TIMING GENERATOR UC1606 contains a built-in system clock. All required components for the clock oscillator are built-in. No external parts are required. DRIVER MODES COM and SEG drivers can be in either Idle mode or Active mode, controlled by Display Enable flag (DC[2]). When COM drivers are in Idle mode, their outputs are high-impedance (open circuit). When SEG drivers are in Idle mode, their outputs are connected to VSS. DRIVER ARRANGEMENTS The naming conventions are: COM(x), where x=1~65, refers to the COM driver for the x-th row of pixels on the LCD panel. The mapping of COM(x) to LCD pixel rows is the same for all MR, MX and MY settings. When MR is not 65, then COM(x) ~ COM65 (X = MR+1) should be left open circuit. Display Controls There are three groups of display control flags in the control register DC: Driver Enable (DE), AllPixel-ON (APO) and Inverse (PXV). DE has the overriding effect over PXV and APO. DRIVER ENABLE (DE) Driver Enable is controlled by the value of DC[2] via Set Display ON command. When DC[2] is set to OFF (logic "0"), both SEG and COM drivers will become idle and UC1606 will put itself into Sleep mode to conserve power. When DC[2] is set to ON, the DE flag will become "1",and UC1606 will first exit from Sleep mode, restore the power (VLCD, VBIAS etc.) and then turn on COM drivers and proper SEG drivers. ALL PIXELS ON (APO) When set, this flag will force all active SEG drivers to output ON signals, disregarding the data stored in the display buffer. This flag has no effect when Display Enable is OFF and it has no effect on data stored in RAM. INVERSE (PXV) When this flag is set to ON, active SEG drivers will output the inverse of the value it received from the display buffer RAM (bit-wise inversion). This flag has no impact on data stored in RAM.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
RAM W/R EO
COM1
COM2
COM3
SEG1
SEG2
Figure 3: COM and SEG Driving Waveform
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003
HOST INTERFACE
As summarized in the table below, UC1606 supports two 8-bit parallel bus protocols and two serial bus protocols. Designers can choose either Bus Type PS[1:0] CS[1:0] CD WR0 WR1 Access D[7:0] 8080 10b 6800 11b the 8-bit parallel bus to achieve high data transfer rate, or use serial bus to create compact LCD modules and minimize connector pins. SPI(S9) 01b - 0
Control & Data Pins
SPI (S8) 00b Chip Select Control/Data
__
___
__
WR
___ __
R/W
0
0 0 EN Read/Write Write Only 8-bit bus (Tri-state) D0=SCK, D2=SDA * Connect unused control pins to VDD or VSS. RD Table 4: Host interfaces Choices
PARALLEL INTERFACE The timing relationship between UC1606 internal control signal RD, WR and their associated bus actions are shown in the figure below. The Display RAM read interface is implemented as a two-stage pipeline. This architecture requires that, every time memory address is modified, either in
External CD ___ WR
parallel mode or serial mode, by either Set CA or Set PA command, a dummy read cycle need to be performed before the actual data can propagate through the pipeline and be read from data port D[7:0]. There is no pipeline in write interface of Display RAM. Data is transferred directly from bus buffer to internal RAM on the rising edges of write pulses.
__
RD D[7:0] LLSB DL DL+K CMSB CLSB Dummy DC DC+1 MMSB MLSB
Internal Write Read Data Latch Column Address L DL L+K DL+K L+K+1 Dummy C DC C+1 DC+1 C+2 DC+2 C+3 M
Figure 4: Parallel Interface & Related Internal Signals
20
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
SERIAL INTERFACE UC1606 supports two serial modes, 4-wire mode (PS="LL"), and 3-wire mode (PS="LH"). The mode of interface is determined during power-up process by the value of PS[1:0]. 4-WIRE SERIAL INTERFACE (S8) Only write operations are supported in 4-wire serial mode. Pin CS[1:0] are used for chip select and bus cycle reset. Pin CD is used to determine the content of the data been transferred. During each write cycle, 8 bits of data, MSB first, are latched on eight rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM on the rising edge of the last SCK pulse. Pin CD is examined when SCK is pulled low for the LSB (D0) of each token.
CS1/0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5
Figure 5.a: 4-wire Serial Interface (S8) 3-WIER SERIAL INTERFACE (S9) Only write operations are supported in 3-wire serial mode. Pin CS[1:0] are used for chip select and bus cycle reset. On each write cycle, the first bit is CD, which determines the content of the following 8 bits of data, MSB first. These 8 command or data bits are latched on rising SCK edges into an 8-bit data holder. If CD=0, the data byte will be decoded as command. If CD=1, this 8-bit will be treated as data and transferred to proper address in the Display Data RAM at the rising edge of the last SCK pulse. By sending CD information explicitly in the bit stream, control pin CD is not used, and should be connected to either VDD or VSS. The toggle of CS0 (or CS1) for each byte of data/command is recommended but optional.
CS0 SDA SCK CD D7 D6 D5 D4 D3 D2 D1 D0 CD D7 D6
Figure 5.b: 3-wire Serial Interface (S9)
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003
HOST INTERFACE REFERENCE CIRCUIT
VDD
VCC D7-D0 CD WR RD D7-D0 CD WR0(WR) WR1(RD)
VDD
MPU
ADDRESS IORQ DECODER VDD VDD
CS0 CS1
UC1606
RST PS1 PS0
GND
VSS
FIGURE 6: 8080/8bit parallel mode reference circuit
VDD
VCC D7-D0 CD R/W E D7-D0 CD WR0(R/W) WR1(E)
VDD
MPU
ADDRESS IORQ DECODER VDD VDD
CS0 CS1
UC1606
RST PS1 PS0
GND
VSS
FIGURE 7: 6800/8bit parallel mode reference circuit
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
VDD
VCC
SCK SDA CD
SCK(D0) SDA(D2) CD WR0 WR1
VDD
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1606
RST PS1 PS0
GND
VSS
FIGURE 8: Serial-8 serial mode reference circuit
VDD
VCC
SCK SDA
SCK(D0) SDA(D2) WR0 WR1
VDD
MPU
ADDRESS IORQ DECODER VDD
CS0 CS1
UC1606
RST VDD PS1 PS0 GND VSS
FIGURE 9: Serial-9 serial mode reference circuit Note: RST pin is optional. When RST pin is not used, connect the pin to VDD.
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003
DISPLAY DATA RAM
DATA ORGANIZATION The display data is 1-bit per pixel and stored in a dual port static RAM (RAM, for Display Data RAM). The RAM size is 65 x 132 for UC1606. This array of data bits is further organized into pages of 8 bit slices to facilitate parallel bus interface. When Mirror X (MX, LC[2]) is OFF, the 1st column of LCD pixels will correspond to the bits of the first byte of each page, the 2nd column of LCD pixels correspond to the bits of the second byte of each page, etc. MSB FIRST OR LSB FIRST There are two options to map D[7:0] to RAM, MSB first (MSF=1), or LSB first (MSF=0), as illustrated in next page. DISPLAY DATA RAM ACCESS The memory used in UC1606 Display Data RAM (RAM) is a special purpose dual port RAM which allows asynchronous access to both its column and row data. Thus, RAM can be independently accessed both for Host Interface and for display operations. DISPLAY DATA RAM ADDRESSING A Host Interface (HI) memory access operation starts with specifying Page Address (PA) and Column Address (CA) by issuing Set Page Address and Set Column Address commands. If wrap-around (WA, AC[0]) is OFF (0), CA will stop increasing after reaching the end of page , and system programmers need to set the values of PA and CA explicitly.
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
MSF PA[3:0] 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7
Line AddeCss 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H SEG132 SEG1 SEG131 SEG2 SEG130 SEG3 SEG129 SEG4 SEG128 SEG5 SEG127 SEG6 SEG126 SEG7 SEG125 SEG8
MY=0 SL=0 SL=16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 CIC SEG128 SEG129 SEG130 SEG131 SEG132 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 CIC
SL=0 C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 CIC 65
MY=1 SL=0 SL=25 SL=25 C48 C25 C47 C24 C46 C23 C45 C22 C44 C21 C43 C20 C42 C19 C41 C18 C40 C17 C39 C16 C38 C15 C37 C14 C36 C13 C35 C12 C34 C11 C33 C10 C32 C9 C31 C8 C30 C7 C29 C6 C28 C5 C27 C4 C26 C3 C25 C2 C24 C1 C23 C64 C22 C63 C21 C62 C20 C61 C19 C60 C18 C59 C17 C58 C16 C57 C15 C56 C14 C55 C13 C54 C12 C53 C11 C52 C10 C51 C9 C50 C8 C49 C7 C48 C6 C47 C5 C46 C4 C45 C3 C44 C2 C43 C1 C42 --C41 --C40 --C39 --C38 --C37 --C36 --C35 --C34 --C33 --C32 --C31 --C30 --C29 --C28 --C27 --C26 CIC CIC 49 65 MUX C9 C8 C7 C6 C5 C4 C3 C2 C1 --------------------------------C48* C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 CIC
0000
Page 0
0001
Page 1
0010
Page 2
0011
Page 3
0100
Page 4
0101
Page 5
0110
Page 6
0111
Page 7
1000
Page 8
49
MX
0
SEG5
SEG4
SEG3
SEG2
Example for memory mapping: let MX = 0, MY = 0, SL = 0, MSF = 0, according to the data shown in the above table: Page 0 SEG 1: 00011111b Page 0 SEG 2: 11001100b
SEG1
1
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High-Voltage Mixed-Signal IC
(c)1999-2003 For the 1st line period of each field Line = SL Otherwise Line = Mod(Line+1, 64) Where Mod is the modular operator, and Line is the bit slice line address of RAM to be outputted to SEG drivers. Line 0 corresponds to the first bit-slice of data in RAM. The above Line generation formula produces the "loop around" effect as it effectively resets Line to 0 when Line+1 reaches 64. Effects such as page scrolling, page swapping can be emulated by changing SL dynamically. MY IMPLEMENTATION Row Mirroring (MY) is implemented by reversing the mapping order between COM electrodes and RAM, i.e. the mathematical address generation formula becomes: For the 1st line period of each field Line = Mod(SL + MUX-1, 64) where MUX = 25, 33, 49, or 65. Otherwise Line = Mod( Line-1 , 64) Visually, the effect of MY is equivalent to flipping the display upside down. The data stored in display RAM is not affected by MY.
MX IMPLEMENTATION Column Mirroring (MX) is implemented by selecting either (CA) or (64-CA) as the RAM column address. Changing MX affects the data written to the RAM. Since MX has no effect on data already stored in RAM, changing MX does not have immediate effect on the displayed pattern. To refresh the display, refresh the data stored in RAM after setting MX. ROW SCANNING For each field, the scanning starts at COM1 through COMx, where x depends on the setting of MR. COM electrode scanning (row scanning) orders are not affected by Start Line (SL) or Mirror Y (MY, LC[3]). When MY is 0, the effect of SL having a value K is to change the mapping of COM1 to the K-th bit slice of data stored in display RAM. Visually, SL having a non-zero value is equivalent to scrolling LCD display up by SL rows. RAM ADDRESS GENERATION The mapping of the data stored in the display SRAM and the scanning electrodes can be obtained by combining the fixed Row scanning sequence and the following RAM address generation formula. During the display operation, the RAM line address generation can be mathematically represented as following:
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
RESET & POWER MANAGEMENT
TYPES OF RESET UC1606 has two different types of Reset: Power-ON-Reset and System-Reset. Power-ON-Reset is performed right after VDD is connected to power. Power-On-Reset will first wait for about ~20mS, depending on the time required for VDD to stabilize, and then trigger the System Reset. System Reset can also be activated by software command or by connecting RST pin to ground. In the following discussions, Reset means System Reset. RESET STATUS When UC1606 enters RESET sequence: * * Operation mode will be "Reset" System Status bits RS and BZ will stay as "1" until the Reset process is completed. When RS=1, the IC will only respond to Read Status command. All other commands are ignored. All control registers are reset to default values. Refer to Control Registers for details of their default values. capacitors, use Reset command to activate the onchip draining circuit. Action Set Driver Enable to "0" Set Driver Enable to "1" Reset command or RST_ pin pulled "L" Power ON Reset Mode Sleep Normal Reset OM 10 11 00
Table 6: OM changes Even though UC1606 consumes very little energy in Sleep mode (typically 5uA or less), since all capacitors are still charged, the leakage through COM drivers may damage the LCD over the long term. It is therefore recommended to use Sleep mode only for brief Display OFF operations, such as full-frame screen updates, and to use RESET for extended screen OFF operations. EXITING SLEEP MODE UC1606 contains internal logic to check whether VLCD and VBIAS are ready before releasing COM and SEG drivers from their idle states. When exiting Sleep or Reset Mode, COM and SEG drivers will not be activated until UC1606 internal voltage sources are restored to their proper values.
*
OPERATION MODES UC1606 has three operating modes (OM): Reset, Normal, Sleep. Mode OM Host Interface Clock LCD Drivers Charge Pump Draining Circuit Reset 00 Active OFF OFF OFF ON Sleep Normal 10 Active OFF OFF OFF OFF 11 Active ON ON ON OFF
Table 5: Operating Modes CHANGING OPERATION MODE In addition to Power-ON Reset, two commands will initiate OM transitions: Set Display Enable, and System Reset. When DC[2] is modified by Set Display Enable, OM will be updated automatically. There is no other action required to enter Sleep mode. For maximum energy utilization, Sleep mode is designed to retain charges stored in external capacitors CB0, CB1, and CL. To drain these
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999-2003 POWER-DOWN SEQUENCE To prevent the charge stored in capacitors CBX+, CBX-, and CL from damaging the LCD when VDD is switched off, use Reset mode to enable the built-in draining circuit and discharge these capacitors. The draining resistor is 1K Ohm for both VLCD and VB+. It is recommended to wait 3 x RC for VLCD and 1.5 x RC for VB+. For example, if CL is 10nF, then the draining time required for VLCD is 3~5mS. When internal VLCD is not used, UC1606 will NOT drain VLCD during RESET. System designers need to make sure external VLCD source is properly drained off before turning off VDD.
POWER-UP SEQUENCE UC1606 power-up sequence is simplified by built-in "Power Ready" flags and the automatic invocation of System-Reset command after Power-ON-Reset. System programmers are only required to wait 20~ 30 ms before the CPU starting to issue commands to UC1606. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands.
Turn on VDD
Reset command
Wait 20~30 mS
Wait 3~5 mS
Set LCD Bias Ratio (BR) Set Gain (GN) Set Potential Meter (PM)
Turn off VDD
Set Display Enable
Figure 10: Reference Power-up Sequence
Figure 11: Reference Power-Down Sequence
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
SAMPLE POWER COMMAND SEQUENCES The following tables are examples of command sequence for power-up, power-down and display ON/OFF operations. These are only to demonstrate some "typical, generic" scenarios. Designers are encouraged to study related sections of the datasheet and find out what the best parameters and control sequences for their specific design needs. C/D W/R Type The type of the interface cycle. It can be either Command (0) or Data (1) The direction of data flow of the cycle. It can be either Write (0) or Read (1). Required: Customer: Advanced: Optional: These items are required These items are not necessary if customer parameters are the same as default We recommend new users to skip these commands and use default values. These commands depend on what users want to do.
POWER-UP Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R C - 0 - 0 - 1 - 1 - 0 - 0 - # - # - 0 Chip action Comments Wait ~30ms after VDD is ON Set up LCD specific parameters such as format, MX, MY, MSF, etc. - Automatic Power-ON Reset. # (16) Set LCD Mapping
C R R C
R
0 0 0 0 1 . . 1 0
0 0 0 0 0 . . 0 0
1 0 1 # # . . # 1
1 0 0 # # . . # 0
1 1 0 # # . . # 1
0 0 0 # # . . # 0
1 0 0 # # . . # 1
0 # 0 # # . . # 1
# # 0 # # . . # 1
# # 1 # # . . # 1
(19) Set Bias Ratio (5) Set Gain (10) Set PM Write display RAM Set up display image
(15) Set Display Enable
POWER-DOWN Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R R 0 - 0 - 1 - 1 - 1 - 0 - 0 - 0 - 1 - Chip action Comments Wait 3~5ms before VDD OFF 0 (17) System Reset - Draining capacitor
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999~2003
BRIEF DISPLAY-OFF Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R C Chip action Comments 0 0 1 0 1 0 1 1 1 0 (15) Set Display Disable # # # # # # # # Write display RAM 0 1 Set up display image (Image update is optional. Data in ........ . . the RAM is retained through ........ . . the SLEEP state.) ######## 0 1 R 0 0 1 0 1 0 1 1 1 1 (15) Set Display Enable * This is only recommended for very brief display OFF (under 10mS). If image becomes unstable use the Extended Display OFF approach shown below.
EXTENDED DISPLAY-OFF Type C/D W/R D7 D6 D5 D4 D3 D2 D1 D0 R - - C 0 - - 0 0 - - 0 1 - - 1 1 - - 1 1 - - 0 0 - - 0 0 - - # 0 - - # 1 - - 0 Chip action Comments CB1, CB1, CLCD discharged. Extended display OFF Zzzz... System waking up Set up LCD specific parameters such as format, MX, MY, MSF, etc. Set up display image (Image update is optional. Data in the RAM is retained through the RESET state.) 0 (17) System Reset. - - # (16) Set LCD Mapping
1 0 # # # # # # # # Write display RAM . . ........ . . ........ 1 0 ######## C 0 0 1 1 1 0 1 0 # # (19) Set Bias Ratio R 0 0 0 0 1 0 0 # # # (5) Set Gain R 0 0 10000001 (10) Set PM 0 0 ######## R 0 0 1 0 1 0 1 1 1 1 (17) Set Display Enable * The sequence is basically the same as the power up sequence, except Power-ON RESET is replaced by System RESET command, and an extended idle time in between.
C
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
ABSOLUTE MAXIMUM RATINGS
In accordance with IEC134, note 1, 2 and 3. Symbol VDD VDD2 VDD3 VLCD VIN TOPR TSTR Logic Supply voltage LCD Generator Supply voltage Analog Circuit Supply voltage LCD Generated voltage Any Input Voltage Operating temperature range Storage temperature Parameter Min. -0.3 -0.3 -0.3 -0.3 -0.3 -30 -55 Max. +5.5 +5.5 +5.5 +15.5 VDD + 0.3 +85 +125 Unit V V V V V
o o
C C
Notes
1. 2. VDD based on VSS = 0V Stress values listed above may cause permanent damages to the device.
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High-Voltage Mixed-Signal IC
(c)1999~2003
SPECIFICATIONS
DC CHARACTERISTICS Symbol VDD VDD2/3 VLCD VD VIL VIH VOL VOH IIL R0(SEG) R0(COM) fCLK Parameter Supply for digital circuit Supply for bias & pump Charge pump output LCD data voltage Input logic LOW Input logic HIGH Output logic LOW Output logic HIGH Input leakage current SEG output impedance COM output impedance Internal clock frequency VLCD = 9V VLCD = 9V 183 3 3.5 190 0.8VDD 1.5 4 4.5 196 0.8VDD 0.2VDD VDD2/3 >= 2.4V, 25 C VDD2/3 >= 2.4V, 25OC
O
Conditions
Min. 2.4 2.4
Typ. 3.0 3.0 9.5
Max. 5.0 5.0 13.5 1.2 0.2VDD
Unit V V V V V V V V A k k kHz
POWER CONSUMPTION VDD = 2.8, Bias Ratio = 9.33, Gain = 1.43, PM = 32, PL = Regular LCD loading, MR = 65, Bus mode = 6800, CL = 20nF, CB = 1uF. All outputs are open-circuit. Display Pattern All-OFF 2-pixel checker Conditions Bus = idle Bus = idle Typ.(A) 249 451 Max.(A) 600 600
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
AC CHARACTERISTICS
CD CS0 CS1 tAS80 tCSSA80 WR0, WR1 Write D[7:0] tACC80 Read D[7:0] Figure 12: Parallel Bus Timing Characteristics (for 8080 MCU) (VDD=2.4V to 3.0V, Ta= -30 to +85 C) Symbol tAS80 tAH80 tCY80 tPWR80 tPWW80 tHPW80 tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSSD80 tCSH80 Signal CD WR1 WR0 WR0, WR1 D0~D7 Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) High pulse width Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 25 50 300 85 85 85 40 15 - 10 15 15 30 Max. - - - - - - 140 100 Units ns ns ns ns ns ns ns ns
o
tAH80 tCY80 tCSH80 tHPW80 tCSSD80
tPWR80, tPWW80
tDS80
tDH80
tOD80
CL = 100pF
CS1/CS0
(VDD=3.0V to 4.0V, Ta= -30 to +85 C) Symbol tAS80 tAH80 tCY80 tPWR80 tPWW80 tHPW80 tDS80 tDH80 tACC80 tOD80 tCSSA80 tCSSD80 tCSH80 Signal CD WR1 WR0 WR0, WR1 D0~D7 Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) High pulse width Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 20 45 166 65 65 65 30 10 - 10 10 10 20 Max. - - - - - - 65 45 Units ns ns ns ns ns ns ns ns
o
CL = 100pF
CS1/CS0
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High-Voltage Mixed-Signal IC
(c)1999~2003
CD CS0 CS1 tAS68 tCSSA68 tCY68 tPWR68, tPWW68 WR1 tDS68 Write D[7:0] tACC68 Read D[7:0] Figure 13: Parallel Bus Timing Characteristics (for 6800 MCU) (VDD=2.4V to 3.0V, Ta= -30 to +85 C) Symbol tAS68 tAH68 tCY68 tPWR68 tPWW68 tLPW68 tDS68 tDH68 tACC68 tOD68 TCSSA68 TCSSD68 TCSH68 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) Low pulse width Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 25 50 300 85 85 85 40 15 - 10 15 15 30 Max. - - - - - - 140 100 Units ns ns ns ns ns ns ns ns
o
tAH68 tCSH68 tLPW68 tCSSD68
tDH68
tOD68
WR1
D0~D7
CL = 100pF
CS1/CS0
(VDD=3.0V to 4.0V, Ta= -30 to +85 C) Symbol tAS68 tAH68 tCY68 tPWR68 tPWW68 tLPW68 tDS68 tDH68 tACC68 tOD68 TCSSA68 TCSSD68 TCSH68 Signal CD Description Address setup time Address hold time System cycle time Pulse width (read) Pulse width (write) Low pulse width Data setup time Data hold time Read access time Output disable time Chip select setup time Condition Min. 20 45 166 65 65 65 30 10 - 10 10 10 20 Max. - - - - - - 70 50 Units ns ns ns ns ns ns ns ns
o
WR1
D0~D7
CL = 100pF
CS1/CS0
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Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
CD CS0 CS1 tASS tCSSAS tCYS tLPWS SCK tDSS SDA Figure 14: Serial Bus Timing Characteristics
o
tAHS tCSHS tHPWS tCSSDS
tDHS
(VDD=2.4V to 3.0V, Ta= -30 to +85 C) Symbol tASS tAHS tCYS tLPWS tHPWS tDSS tDHS tCSSAS tCSSDS tCSHS Signal CD Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 15 40 250 100 100 90 90 10 10 150 Max. - - - - - - Units ns ns ns ns ns ns ns
SCK SDA CS1/CS0
(VDD=3.0V to 4.0V, Ta= -30 to +85 C) Symbol tASS tAHS tCYS tLPWS tHPWS tDSS tDHS tCSSAS tCSSDS tCSHS Signal CD Description Address setup time Address hold time System cycle time Low pulse width High pulse width Data setup time Data hold time Chip select setup time Condition Min. 10 20 200 75 75 50 50 10 10 100 Max. - - - - - - Units ns ns ns ns ns ns ns
o
SCK SDA CS1/CS0
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ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999~2003
tRW RST
Figure 15: Reset Characteristics
o
(VDD=2.4V to 3.0V, Ta= -30 to +85 C) Symbol tRW Signal RST Description Reset low pulse width
o
Condition
Min. 240
Max. -
Units ns
(VDD=3.0V to 4.0V, Ta= -30 to +85 C) Symbol tRW Signal RST Description Reset low pulse width Condition Min. 200 Max. - Units ns
36
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
PHYSICAL DIMENSIONS
DIE SIZE:
9.862 mm x 1.647 mm
DIE THICKNESS:
0.625mm
BUMP HEIGHT:
17m 1m (within die)
AU BUMP SIZE:
86 X 46m2 (Typ.) 2 66 x 49m (Typ.)
MINIMUM BUMP PITCH:
70m (Typ.)
MINIMUM BUMP GAP:
24m (Typ.)
COORDINATE ORIGIN:
Chip center
PAD REFERENCE:
Pad center (Drawings and coordinates are in the circuit/bump view)
Version 1.32
37
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999~2003
ALIGNMENT MARK INFORMATION
(0,0)
D-Left Mark
SHAPE OF THE ALIGNMENT MARK:
R C r
D-Right Mark
NOTE: Alignment mark is on Metal3 under Passivation.
COORDINATES: D-Left Mark Center X -4610.0 Y -430.7 D-Right Mark Center X 4610.0 Y -430.7
SIZE: R: 18.0 m; r: 9.0 m
TOP METAL AND PASSIVATION:
FOR NON-OTP PROCESS CROSS-SECTION
38
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
PAD COORDINATES
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Name COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 CIC NC EO VDDX CS0 CS1 TST4 RST CD WR0 WR1 D0 D1 D2 D3 D4 D5 X -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4813 -4612 -4542 -4472 -4402 -4332 -4262 -4192 -4122 -4052 -3982 -3912 -3842 -3764 -3694 -3624 -3554 -3484 -3414 -3344 -3274 -3204 -3134 -3064 -2994 -2924 -2854 -2784 -2714 Y 698 628 558 488 418 348 278 208 138 68 -2 -72 -142 -212 -282 -352 -422 -492 -562 -632 -702 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 W 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 H 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 # 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 Name D6 D7 VDD VDD VDD VDD VDD VDD2 VDD2 VDD2 VDD2 VDD3 VSS VSS VSS VSS VSS VSS2 VSS2 VSS2 VSS2 VB1+ VB1+ VB1+ TP3 TP2 TP1 PS0 PS1 VDDX MR0 MR1 VB1VB1VB1VB1VB0VB0VB0VB0BR0 BR1 VDDX TC0 TC1 VB0+ VB0+ VB0+ VB0+ X -2644 -2574 -2394 -2287 -2180 -2074 -1967 -1769 -1663 -1556 -1449 -1343 -1054 -947 -841 -734 -627 -430 -323 -216 -110 125 231 338 436 526 616 764 904 974 1114 1254 1394 1464 1534 1604 1744 1814 1884 1954 2094 2234 2304 2444 2584 2724 2794 2864 2934 Y -706 -706 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -723 -724 -724 -724 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 W 46 46 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 66 66 66 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 H 86 86 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 49 49 49 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Version 1.32
39
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999~2003 Y -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -706 -702 -632 -562 -492 -422 -352 -282 -212 -142 -72 -2 68 138 208 278 348 418 488 558 628 698 706 706 706 706 706 706 706 706 706 W 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 46 46 46 46 46 46 46 46 46 H 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 86 86 86 86 86 86 86 86 86 # 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Name SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 X 3955 3885 3815 3745 3675 3605 3535 3465 3395 3325 3255 3185 3115 3045 2975 2905 2835 2765 2695 2625 2555 2485 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 945 875 805 735 665 595 525 455 Y 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 W 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 H 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
# 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149
Name TST1 TST2 TST3 VLCDIN VLCDOUT VLCDIN VLCDOUT VDD2 VDD2 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM46 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 CIC SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
X 3074 3144 3214 3354 3424 3494 3634 3704 3774 3844 3914 3984 4054 4124 4194 4264 4334 4404 4474 4544 4614 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4813 4585 4515 4445 4375 4305 4235 4165 4095 4025
40
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
# 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251
Name SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111
X 385 315 245 175 105 35 -35 -105 -175 -245 -315 -385 -455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2485 -2555 -2625 -2695 -2765 -2835 -2905 -2975 -3045 -3115
Y 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706
W 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46
H 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
# 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272
Name SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132
X -3185 -3255 -3325 -3395 -3465 -3535 -3605 -3675 -3745 -3815 -3885 -3955 -4025 -4095 -4165 -4235 -4305 -4375 -4445 -4515 -4585
Y 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706 706
W 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46 46
H 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86 86
Version 1.32
41
(c)1999~2003
High-Voltage Mixed-Signal IC
TRAY INFORMATION
ULTRACHIP
Remark: 1.UC1606 Die Size :9.862*1.647*0.635mm (after wafer sawing, include scribeline dimension) 2.Surface resistivity: 1*10 ~10 /cm
Unless Otherwise Specified Unit General Roughness Tolerance Dimension Angle
see drawing detail
mm N/A
ULTRA CHIP INC.
Scale
N/A
Proj.
Package Code
UC1606 IC Tray
Material
Type:H20-393*70-32(60)
Drawn By N/A Date Iris Chen 07-04-02'
Checked
Approved
Drawing No
Rev.
Alvin Chang
Alvin Chang
B
07-04-02'
07-04-02'
Sheet
1 of 1
Size
A4
42
Product Specifications
UC1606
65x132 Matrix LCD Controller-Drivers
REVISION HISTORY
Version 1.0 1.1 1.2 Contents First release Frame rate increased, AC/DC Characteristics update, Product naming rule added Operation Voltage up to 5.0V Over All revision (1) Recommended CL value is adjusted to 5nF ~ 20nF (Page 5) (2) VDD1 is renamed to VDD (Page 5) (3) TP3 is renamed to TST4 (Page 7) (4) TP[2:0] is renamed to TP[3:1] (Page 7) 1.3 (5) C[0:131] is renamed to SEG[1:132] (Page 7) (6) R[1~64] is renamed to COM[1~64] (Page 7) (7) RIC is renamed to CIC (Page 7) (8) Application circuits are added. (Page 18, 23, 24) (9) Alignment Mark Information is presented (Page 39) (10) Tray Information is presented. (Page 43) (11) Power Consumption table is presented (Page 33) (1) The direction on dealing with unused bus pins is corrected as leaving open-circuit; instead of connecting to VDD/VSS. (Section "Pin Description", page 6; "Host Interface", page 21.) (2) Figures 8 and 9, reference circuit for S8/S9, are corrected to present SDA=D2, instead of D3. 1.31 (Section "Host interface reference circuit", Page 24) (3) "Power Consumption" table is filled with data. (Section "Specifications", Page 33) (4) Figures 12, 13 and 14 are patched by adding pulse CS1. (Section "AC Characteristics", Pp 33-35) Jun. 18, 2003 Aug. 16, 2002 Date of Rev. Jul. 06, 2001 Oct. 30, 2001 Dec. 18, 2001
Version 1.32
43
ULTRACHIP
High-Voltage Mixed-Signal IC
(c)1999~2003
Version
Contents (1) Section "Table of Revision History" is renamed as "Revision History" and moved to the rear of the datasheet. (2) Recommended CB value has been modified: ~ 100x (Section "Pin Description", page 4) 150 ~ 250x
Date of Rev.
(3) In the "Bits" column, number of bit is updated from "PIN" to "2" (Section "Control Registers" - "MR" entry, page 7) (4) In the "Default" column, the default values are updated: "00H" "0H" (Section "Control Registers" - entries "DC", "AC", and "LC", page 8) (5) In the "Default value" column, the default value is updated: "0011b" "011b" (Section "Command Table" - (5) Set Gain, page 9) (6) Description of PC[2:1] is modified: 00b: 4x 01b: 4x (Section "Control Register", page 9; "Command Description", page 11) (7) The description for MX is updated: MX: Status of register LC[1] LC[2] (Section "Command Description" - (3) Get Status, page 10) (8) In the Action column, pin specifying is updated: Set APC[1:0] APC[0] (Section "Command Description" - (7) Set Advance Product Configuration, page 11) (9) The value of pins D[7:4] is corrected: 0110 1011 (Section "Command Description" - (9) Set Page Address, page 11) (10) The values of WR0/WR1 of SPI(S8)/SPI(S9) are updated: "-" "0" (Section "Host Interface" - Table 4, page 20) (11) Figure 6/7: 8080/8bit and 6800/8bit parallel mode reference circuit is modified by showing RST pin. Figure 8/9: Serial-8/9 serial mode reference circuit is modified as following: SDA(D3) SDA(D2) (Section "Host interface reference circuit", Pp 22 - 23) (12) Power consumption table is added. (Section "Specifications", page 32) (13) Die Size is updated. (Section "Physical Dimensions", page 37) (14) Alignment Mark Information is updated. (Section "Alignment Mark Dimension", page 38)
1.32
Sep. 24, 2003
44
Product Specifications

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